Interactions of Technology and Design in Nanoscale SRAM

Continued advances in silicon technology have enabled the VLSI industry to shrink the area of the transistor by roughly a factor of two with each successive technology node. This trend has continued unabated for the past five decades and has made personal computing devices ubiquitous in modern culture. Made possible by continuous advances in CMOS technology and fueled by a growing and fiercely competitive market, in order for this trend to continue, continued advances in CMOS process technology as well as circuit design innovation are required. Reduced device dimensions and operating voltages that accompany technology scaling have led to increased design challenges with each successive technology node. Thus, reduced functional yield margins coupled with increasing variability of the CMOS device characteristics have become the most significant problem facing future nanoscale SRAM, motivating this effort. To address these challenges, a custom scaled (90nm-22nm) predictive technology model